Presentation | 1995/11/21 A Low-power Synchronous SRAM Macrocell with Column-address Controlled Virtual-GND lines Nobutaro SHIBATA, Mayumi WATANABE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Circuit techniques for low-power and fast SRAM macrocells were described. A low-power memory cell with a virtual-GND line whose level was controlled by column-select signals and a WE-signal was proposed. A fast write scheme with above memory cells was also mentioned. A current-mode fast sense amplifier was devised to improve its switching speed. A synchronous SRAM-macrocell test chip was designed and fabricated with 0.5-μm single-polysilicon double-metal CMOS technology. The low static-power of 360-μA/bit and 190-MHz operation at 3.3-V were demonstrated by 4K-word SRAM's. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | ASIC / macrocell / SRAM / low-power / fast / virtual-GND |
Paper # | SDM95-161 |
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Conference Information | |
Committee | SDM |
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Conference Date | 1995/11/21(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Low-power Synchronous SRAM Macrocell with Column-address Controlled Virtual-GND lines |
Sub Title (in English) | |
Keyword(1) | ASIC |
Keyword(2) | macrocell |
Keyword(3) | SRAM |
Keyword(4) | low-power |
Keyword(5) | fast |
Keyword(6) | virtual-GND |
1st Author's Name | Nobutaro SHIBATA |
1st Author's Affiliation | NTT LSI Laboratories() |
2nd Author's Name | Mayumi WATANABE |
2nd Author's Affiliation | NTT LSI Laboratories |
Date | 1995/11/21 |
Paper # | SDM95-161 |
Volume (vol) | vol.95 |
Number (no) | 379 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |