Presentation | 1996/5/23 Simulation for Degradation of Flash Memory due to Charge Traps in the Tunnel Oxide Ayumi Yokozawa, Hiroki Shirai, Takeshi Okazawa, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The degradation of the endurance and retention Characteristics of flash memories is predicted to be induced by charge trapping in the tunnel oxides generated during FN programming and erasing operations. In this paper, the generation of the oxide charge traps are deduced from the results of electrical measurements of simple MOS devices, and the degradation of the endurance and retention characteristics due to the generated charge traps have been simulated. The simulation results indicate that the reduction of FN current due to electron traps in the tunnel oxides degrades the endurance characteristics. The tunnel leakage current through the electron traps degrades the retention characteristics, and hole traps near the oxides/substrate interface increase this tunnel leakage current. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Flash Memories / Computer Simulation / Tunnel Oxides / Charge Trapping States FN Programming/Erasing / Endurance Characteristics / Retention Characteristics |
Paper # | SDM96-18 |
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Conference Information | |
Committee | SDM |
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Conference Date | 1996/5/23(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Simulation for Degradation of Flash Memory due to Charge Traps in the Tunnel Oxide |
Sub Title (in English) | |
Keyword(1) | Flash Memories |
Keyword(2) | Computer Simulation |
Keyword(3) | Tunnel Oxides |
Keyword(4) | Charge Trapping States FN Programming/Erasing |
Keyword(5) | Endurance Characteristics |
Keyword(6) | Retention Characteristics |
1st Author's Name | Ayumi Yokozawa |
1st Author's Affiliation | NEC ULSI Device Development Laboratories() |
2nd Author's Name | Hiroki Shirai |
2nd Author's Affiliation | NEC ULSI Device Development Laboratories |
3rd Author's Name | Takeshi Okazawa |
3rd Author's Affiliation | NEC Memory Division |
Date | 1996/5/23 |
Paper # | SDM96-18 |
Volume (vol) | vol.96 |
Number (no) | 63 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |