| Presentation | 1996/8/23 The Charge-Share Modified Precharge-Level (CSM) Architecture for High-Speed and Low-Power Ferroelectric Memory Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A Charge-Share Modified precharge-level (CSM) architecture is proposed for ferroelectric memories that reduces memory-array current to less than 1% that in conventional architectures while maintaining high-speed operation. A self-timing precharge technique solves the polarization disturbance problem in this architecture without adding extra signal lines or timing margin. This architecture achieves low-power, high-density, high-speed, and high-operating-margin simultaneously, making it a leading candidate for use in high-density ferroelectric memories. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ferroelectric memory / Nonvolatile / Low-power / High-speed |
| Paper # | SDM-96-85,ICD-96-105 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1996/8/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Charge-Share Modified Precharge-Level (CSM) Architecture for High-Speed and Low-Power Ferroelectric Memory |
| Sub Title (in English) | |
| Keyword(1) | Ferroelectric memory |
| Keyword(2) | Nonvolatile |
| Keyword(3) | Low-power |
| Keyword(4) | High-speed |
| 1st Author's Name | Hiroki Fujisawa |
| 1st Author's Affiliation | Device Development Center, Hitachi Ltd.() |
| 2nd Author's Name | Takeshi Sakata |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi Ltd. |
| 3rd Author's Name | Tomonori Sekiguchi |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi Ltd. |
| 4th Author's Name | Osamu Nagashima |
| 4th Author's Affiliation | Device Development Center, Hitachi Ltd. |
| 5th Author's Name | Katsutaka Kimura |
| 5th Author's Affiliation | Central Research Laboratory, Hitachi Ltd. |
| 6th Author's Name | Kazuhiko Kajigaya |
| 6th Author's Affiliation | Device Development Center, Hitachi Ltd. |
| Date | 1996/8/23 |
| Paper # | SDM-96-85,ICD-96-105 |
| Volume (vol) | vol.96 |
| Number (no) | 226 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |