| Presentation | 1996/8/23 6F^2 Layout DRAM Cell with Lithography-Oriented Design Masami Aoki, Tohru Ozaki, Takashi Yamada, Hitomi Kawaguchiya, Yutaka Ishibashi, Takeshi Hamamoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel BOC (Bit-line Over Capacitor) cell for low cost 1Gb DRAM is proposed. By a 6F^2 open bit-line cell layout and a dual isolation structure, active region was designed with a simple line-and-space configuration offering a large lithography process margin. A self-aligned cylindrical stacked capacitor and a bit line plug fabrication process were developed in order to obtain sufficient storage capacity and a large alignment tolerance. A test structure was made using the 0.4-μm design rule and cell characteristics were investigated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / stacked capacitor / lithography / self-aligned process |
| Paper # | SDM-96-84,ICD-96-104 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 1996/8/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 6F^2 Layout DRAM Cell with Lithography-Oriented Design |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | stacked capacitor |
| Keyword(3) | lithography |
| Keyword(4) | self-aligned process |
| 1st Author's Name | Masami Aoki |
| 1st Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation() |
| 2nd Author's Name | Tohru Ozaki |
| 2nd Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation |
| 3rd Author's Name | Takashi Yamada |
| 3rd Author's Affiliation | ULSI Research Laboratories, Toshiba Corporation |
| 4th Author's Name | Hitomi Kawaguchiya |
| 4th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation |
| 5th Author's Name | Yutaka Ishibashi |
| 5th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation |
| 6th Author's Name | Takeshi Hamamoto |
| 6th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation |
| Date | 1996/8/23 |
| Paper # | SDM-96-84,ICD-96-104 |
| Volume (vol) | vol.96 |
| Number (no) | 226 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |