Presentation 1996/7/19
Circuit Technologies for High-Endurance, Low-Power Nonvolatile DRAMs
Tomonori Sekiguchi, Takeshi Sakata, Hiroki Fujisawa, Kazuyoshi Torii, Kazuhiko Kajigaya, Katsutaka Kimura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Improved endurance and reduced power consumption are key design issues in implementing ferroelectric nonvolatilc memories. A proposed small data-line-swing read/write scheme improves the write endurance by almost three orders of magnitude. A doubled data-line-capacitance recall scheme reduces the array power in the normal read/write operation to one-third that of the conventional nonvolatile DRAM.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ferroelectric / nonvolatile memory / DRAM / fatigue / small data-line-swing
Paper # SDM96-62,ICD96-82
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Conference Information
Committee SDM
Conference Date 1996/7/19(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Circuit Technologies for High-Endurance, Low-Power Nonvolatile DRAMs
Sub Title (in English)
Keyword(1) ferroelectric
Keyword(2) nonvolatile memory
Keyword(3) DRAM
Keyword(4) fatigue
Keyword(5) small data-line-swing
1st Author's Name Tomonori Sekiguchi
1st Author's Affiliation Central Research Laboratory, Hitachi Ltd.()
2nd Author's Name Takeshi Sakata
2nd Author's Affiliation Central Research Laboratory, Hitachi Ltd.
3rd Author's Name Hiroki Fujisawa
3rd Author's Affiliation Device Development Center, Hitachi Ltd.
4th Author's Name Kazuyoshi Torii
4th Author's Affiliation Central Research Laboratory, Hitachi Ltd.
5th Author's Name Kazuhiko Kajigaya
5th Author's Affiliation Device Development Center, Hitachi Ltd.
6th Author's Name Katsutaka Kimura
6th Author's Affiliation Central Research Laboratory, Hitachi Ltd.
Date 1996/7/19
Paper # SDM96-62,ICD96-82
Volume (vol) vol.96
Number (no) 152
Page pp.pp.-
#Pages 8
Date of Issue