Presentation 1996/11/15
Fully Self-aligned Metalization MOSFET using selective AI CVD technology
A. Gotoh, H. Matsuhashi, R. Tajima, Y. Yokoyama, K. Masu, K. Tsubouchi,
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Abstract(in English) Parasitic resistance of Gate/Source/Drain regions degrade the device performance of deep-submicron MOSFET circuits. We have proposed Fully Self-Aligned Metalization (FSAM) MOSFET using selective AI-CVD technology. The features are (1) low TiSi_2/Si contact resistance, (2) AI and TiSi_2 diffusion barrier layer and (3) selective CVD AI layer for low sheet resistance. In this work, we report the self-aligned barrier layer formation using low temperature N_2 plasma nitridation on TiSi_2 surface.
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Keyword(in English) FSAMMOSFET / selective AI-CVD / barrier layer / N_2 plasma nitridation
Paper # SDM96-135
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Committee SDM
Conference Date 1996/11/15(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fully Self-aligned Metalization MOSFET using selective AI CVD technology
Sub Title (in English)
Keyword(1) FSAMMOSFET
Keyword(2) selective AI-CVD
Keyword(3) barrier layer
Keyword(4) N_2 plasma nitridation
1st Author's Name A. Gotoh
1st Author's Affiliation Reseach Institute of Electrical Communication, Tohoku university()
2nd Author's Name H. Matsuhashi
2nd Author's Affiliation Reseach Institute of Electrical Communication, Tohoku university
3rd Author's Name R. Tajima
3rd Author's Affiliation Reseach Institute of Electrical Communication, Tohoku university
4th Author's Name Y. Yokoyama
4th Author's Affiliation Reseach Institute of Electrical Communication, Tohoku university
5th Author's Name K. Masu
5th Author's Affiliation Reseach Institute of Electrical Communication, Tohoku university
6th Author's Name K. Tsubouchi
6th Author's Affiliation Reseach Institute of Electrical Communication, Tohoku university
Date 1996/11/15
Paper # SDM96-135
Volume (vol) vol.96
Number (no) 360
Page pp.pp.-
#Pages 6
Date of Issue