| Presentation | 1997/7/24 A CAD-Compatible SOI/CMOS Gate Array having Body-Fixed Partially-Depleted Transistors Kimio Ueda, Koji Nii, Yoshiki Wada, Takanori Hirota, Shigenobu Maeda, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Shigeto Maegawa, Koichiro Mashiko, Hisanori Hamano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Thin film SOI/CMOS devices are attractive candidates for low-voltage and low-power VLSIs because of their reduced junction capacitances and back-gate bias effects. However, problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time have prevented partially-depleted SOI/CMOS devices from being commercially used. This paper describes a 0.35μm 220KG SOI/CMOS gate array using partially-depleted devices that overcomes the above problems and allows the use of cell libraries and design methodologies compatible with bulk/CMOS gate arrays by optimizing the basic-cell layout and power-line wiring. The SOI/CMOS gate array operates at 2.0V consuming 65% less power than a typical 0.35μm 3.3V bulk/CMOS gate array. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SOI/CMOS device / Gate array / Partially-depleted device |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1997/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A CAD-Compatible SOI/CMOS Gate Array having Body-Fixed Partially-Depleted Transistors |
| Sub Title (in English) | |
| Keyword(1) | SOI/CMOS device |
| Keyword(2) | Gate array |
| Keyword(3) | Partially-depleted device |
| 1st Author's Name | Kimio Ueda |
| 1st Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp.() |
| 2nd Author's Name | Koji Nii |
| 2nd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 3rd Author's Name | Yoshiki Wada |
| 3rd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 4th Author's Name | Takanori Hirota |
| 4th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 5th Author's Name | Shigenobu Maeda |
| 5th Author's Affiliation | ULSI Laboratory, Mitsubishi Electric Corp. |
| 6th Author's Name | Toshiaki Iwamatsu |
| 6th Author's Affiliation | ULSI Laboratory, Mitsubishi Electric Corp. |
| 7th Author's Name | Yasuo Yamaguchi |
| 7th Author's Affiliation | ULSI Laboratory, Mitsubishi Electric Corp. |
| 8th Author's Name | Takashi Ipposhi |
| 8th Author's Affiliation | ULSI Laboratory, Mitsubishi Electric Corp. |
| 9th Author's Name | Shigeto Maegawa |
| 9th Author's Affiliation | ULSI Laboratory, Mitsubishi Electric Corp. |
| 10th Author's Name | Koichiro Mashiko |
| 10th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 11th Author's Name | Hisanori Hamano |
| 11th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| Date | 1997/7/24 |
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| Volume (vol) | vol.97 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 7 |
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