| Presentation | 1997/7/24 A DRAM Refresh Architecture for Merged DRAM/Logic LSIs Koji KAI, Taku OHSAWA, Kazuaki MURAKAMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We address the issues on DRAM refreshes in merged DRAM/logic LSIs, and investigate the impact of refreshes on performance and power consumption. Two facts can be drawn from the results of the investigation. Firstly, even if the data retention time is shortened by 10%, there are less impacts on the performance and the power consumption. Based on this, making merged DRAM/logic LSIs with low cost by applying the conventional logic process technology is becoming rearistic. Secondly, the refresh penalty is heavy for very short data retention times. Taking these into considerration, we propose a refresh architecture and methodologies to reduce the refresh penalty in merged DRAM/logic LSIs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | merged DRAM/logic LSI / processor / refresh / power consumption / performance |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1997/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DRAM Refresh Architecture for Merged DRAM/Logic LSIs |
| Sub Title (in English) | |
| Keyword(1) | merged DRAM/logic LSI |
| Keyword(2) | processor |
| Keyword(3) | refresh |
| Keyword(4) | power consumption |
| Keyword(5) | performance |
| 1st Author's Name | Koji KAI |
| 1st Author's Affiliation | Institute of Systems & Information Technologies KYUSHU() |
| 2nd Author's Name | Taku OHSAWA |
| 2nd Author's Affiliation | Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University |
| 3rd Author's Name | Kazuaki MURAKAMI |
| 3rd Author's Affiliation | Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 1997/7/24 |
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| Volume (vol) | vol.97 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 8 |
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