| Presentation | 1997/7/24 High Speed Circuit Design with Matched Delay Technique Jin- Ku Kang, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The matched delay technique is a timing methodology for clock and data delay coordination that produces very high performance integrated circuits. In this methodology, control of path propagation delays combined with careful management of clock skew and data events, is used to design very high speed circuits. In this paper, a CMOS data recovery circuit design based on the matched delay technique is presented. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | matched delay / circuit design / clock / data recovery / CMOS |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1997/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Speed Circuit Design with Matched Delay Technique |
| Sub Title (in English) | |
| Keyword(1) | matched delay |
| Keyword(2) | circuit design |
| Keyword(3) | clock |
| Keyword(4) | data recovery |
| Keyword(5) | CMOS |
| 1st Author's Name | Jin- Ku Kang |
| 1st Author's Affiliation | Department of Electronic, Electrical and Computer Engineering Inha University() |
| Date | 1997/7/24 |
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| Volume (vol) | vol.97 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 6 |
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