Presentation | 1997/7/24 A Multi-Page Cell Architecture for High-Speed Programming Multi-Level NAND Flash Memories Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A multi-page cell architecture is proposed, which enables the fastest programming without area penalty. The proposed four-level cell contains two "pages" which correspond to two X-addresses, X1 and X2 and the programming of X1 and that of X2 are performed at different operations. The program speed is 236us/512byte or 2.2Mbyte/sec, which is 2.3 times faster than a conventional scheme because both the number of program pulses and that of the verify read sequences are reduced. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Flash memory / multilevel cell / NAND EEPROM / High speed programming |
Paper # | SDM97-59 |
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Conference Information | |
Committee | SDM |
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Conference Date | 1997/7/24(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Multi-Page Cell Architecture for High-Speed Programming Multi-Level NAND Flash Memories |
Sub Title (in English) | |
Keyword(1) | Flash memory |
Keyword(2) | multilevel cell |
Keyword(3) | NAND EEPROM |
Keyword(4) | High speed programming |
1st Author's Name | Ken Takeuchi |
1st Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation() |
2nd Author's Name | Tomoharu Tanaka |
2nd Author's Affiliation | Memory Division, Toshiba Corporation |
3rd Author's Name | Toru Tanzawa |
3rd Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Corporation |
Date | 1997/7/24 |
Paper # | SDM97-59 |
Volume (vol) | vol.97 |
Number (no) | 195 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |