| Presentation | 1997/7/24 Analysis of Dopant Interdiffusion and Parasitics Reduction on a-Si/Ti Local Wiring Scheme Jiro Ida, Atsushi Ohtomo, Kouichi Morikawa, Hiroshi Onoda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The a-Si/Ti local wiring technology is characterized from the viewpoints of dopant interdiffusion behavior and parasitics reduction. It was founded that only p+/njunction degrades with the TiSi2 local wiring connecting n+layer and p+layer. The results of electrical measurement with a set of new test patterns suggest the reason, that is, the boron dose not diffuse from TiSi_2 to Sidue to high efficiency of TiB formation. The effect of parasitics reduction on the practical circuit of the 54bit x 2K dual-port SRAM macro was comparatively analyzed with and without TiSi2 local wiring scheme. The area reduction of 31% and the total power reduction of 15.2% was obtained. It was emphasized the reduction of junction capacitance with the local wiring scheme is beneficial to low voltage / low power circuit applications in sub half micron CMOS. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | TiSi2 / local wiring / salicide / SRAM |
| Paper # | SDM97-45 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1997/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis of Dopant Interdiffusion and Parasitics Reduction on a-Si/Ti Local Wiring Scheme |
| Sub Title (in English) | |
| Keyword(1) | TiSi2 |
| Keyword(2) | local wiring |
| Keyword(3) | salicide |
| Keyword(4) | SRAM |
| 1st Author's Name | Jiro Ida |
| 1st Author's Affiliation | VLSI R&D Center, OKI Electric Industry Co., Ltd.() |
| 2nd Author's Name | Atsushi Ohtomo |
| 2nd Author's Affiliation | VLSI R&D Center, OKI Electric Industry Co., Ltd. |
| 3rd Author's Name | Kouichi Morikawa |
| 3rd Author's Affiliation | VLSI R&D Center, OKI Electric Industry Co., Ltd. |
| 4th Author's Name | Hiroshi Onoda |
| 4th Author's Affiliation | VLSI R&D Center, OKI Electric Industry Co., Ltd. |
| Date | 1997/7/24 |
| Paper # | SDM97-45 |
| Volume (vol) | vol.97 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |