Presentation 1998/11/17
Integrated circuit based on neural network which generates limit cycle
Tomohiro Yamana, Yoshihiro Hayakawa, Kouji Nakajima, Yasuji Sawada,
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Abstract(in English) Dynamical information processing is often observed in living systems. Walking is a typical example of this kind of processing, and heart beating is thought to be a clock which is most important for life. How is this kind of processing generated in our body? Recently there have been reported that chaos and limit cycle can be generated in neural networks with asymmetric connection. In this report, a neural network which generates limit cycle has been integrated on a silicon chip. The Input-Output logic function is realized according to the Input-Output property of neuron function. And the memory circuit is constructed by D-FF with an SRAM like circuit. The integrated neural network consists of eight neuron units has been construted.
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Keyword(in English) neural networks / asymmetric connection / limit cycle / integrated circuit
Paper # NC98-54
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Committee NC
Conference Date 1998/11/17(1days)
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Registration To Neurocomputing (NC)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Integrated circuit based on neural network which generates limit cycle
Sub Title (in English)
Keyword(1) neural networks
Keyword(2) asymmetric connection
Keyword(3) limit cycle
Keyword(4) integrated circuit
1st Author's Name Tomohiro Yamana
1st Author's Affiliation Research Institute of Electrical Communication, Tohoku University()
2nd Author's Name Yoshihiro Hayakawa
2nd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
3rd Author's Name Kouji Nakajima
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
4th Author's Name Yasuji Sawada
4th Author's Affiliation Research Institute of Electrical Communication, Tohoku University
Date 1998/11/17
Paper # NC98-54
Volume (vol) vol.98
Number (no) 401
Page pp.pp.-
#Pages 6
Date of Issue