Presentation 1997/3/17
Self - Organized Arrangement for Feature Extraction mechanism by analog circuit
Daisaku Sudou, Tetsuya Asai, Hitoshi Ikeda, Takayasu Sugiura, Kiyotaka Tsuji, Naoki Ohshima, Jang-Kyoo Shin, Hiroo Yonezu,
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Abstract(in English) In the analog implementation of artificial neural networks, variation of device characteristics is known to be detrimental to the correct operations of those networks. In order to resolve such a problem caused by device mismatches, we had proposed a new network model and a new algorithm for unsupervised learning based on Kohonen's topological mapping theory. We fabricated neural circuits forming a topological map(a feature map). Experimental characteristics were in good agreement with computer simulation results. Desired correction signals for the proposed learning emerged from the network. The results showed the possibility of successful self - organization of the topological map in the analog network.
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Keyword(in English) analog network / device mismatch / feature map
Paper # NC96-116
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Committee NC
Conference Date 1997/3/17(1days)
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Registration To Neurocomputing (NC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Self - Organized Arrangement for Feature Extraction mechanism by analog circuit
Sub Title (in English)
Keyword(1) analog network
Keyword(2) device mismatch
Keyword(3) feature map
1st Author's Name Daisaku Sudou
1st Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology()
2nd Author's Name Tetsuya Asai
2nd Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
3rd Author's Name Hitoshi Ikeda
3rd Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
4th Author's Name Takayasu Sugiura
4th Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
5th Author's Name Kiyotaka Tsuji
5th Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
6th Author's Name Naoki Ohshima
6th Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
7th Author's Name Jang-Kyoo Shin
7th Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
8th Author's Name Hiroo Yonezu
8th Author's Affiliation Department of Electrical and Electronic Engineering, Toyohashi University of Technology
Date 1997/3/17
Paper # NC96-116
Volume (vol) vol.96
Number (no) 583
Page pp.pp.-
#Pages 6
Date of Issue