Presentation 2000/4/26
Digital SQUID based on DROS with flux locked loop circuit consisting of 4JL Up/Down counter and R-2R ladder-type D/A converter
H. Myoren, M. Nakamura, T. Iizuka, S. Takada,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have designed a digital SQUID based on a double relaxation oscillation SQUID (DROS) with a flux locked loop (FLL) circuit consisting of an Up/Down counter and a D/A converter. The Up/Down counter was designed using 4JL gates operated with 2-phase power system. The D/A converter was designed using the R-2R ladder-type D/A converter. We simulated dynamic behavior of a DROS with a FLL circuit combined with the Up/Down counter and the D/A converter. Simulation results showed correct flux locked behavior and large slew rate of 10^7 Φ_0/s for the digital SQUID.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Digital SQUID / DROS / 4JL Up/Down counter / R-2R ladder-type D/A converter
Paper # SCE2000-8
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Conference Information
Committee SCE
Conference Date 2000/4/26(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Digital SQUID based on DROS with flux locked loop circuit consisting of 4JL Up/Down counter and R-2R ladder-type D/A converter
Sub Title (in English)
Keyword(1) Digital SQUID
Keyword(2) DROS
Keyword(3) 4JL Up/Down counter
Keyword(4) R-2R ladder-type D/A converter
1st Author's Name H. Myoren
1st Author's Affiliation Faculty of Engineering, Saitama University()
2nd Author's Name M. Nakamura
2nd Author's Affiliation Faculty of Engineering, Saitama University
3rd Author's Name T. Iizuka
3rd Author's Affiliation Faculty of Engineering, Saitama University
4th Author's Name S. Takada
4th Author's Affiliation Faculty of Engineering, Saitama University
Date 2000/4/26
Paper # SCE2000-8
Volume (vol) vol.100
Number (no) 24
Page pp.pp.-
#Pages 6
Date of Issue