Presentation 2000/4/26
Design of a RSFQ Demultiplexer Based on the Shift-and-Dump Architecture
Masaaki Maezawa, Motohiro Suzuki, Akira Shoji,
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Abstract(in English) We designed and implemented a RSFQ demultiplexer (DMUX) based on the shift-and-dump architecture. A pipeline structure was introduced into the control circuit and a destructive-readout cell was used as a unit cell of the shift register, which made synchronization easier and improved throughput of the circuit. Calculated margins for the bias currents of the DMUX were as large as +/-28 % at clock frequency of 10 GHz. A 4-stage shift register with parallel outputs, a main component of the DMUX, was fabricated and successfully tested.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) demultiplexer / serial-to-parallel conversion / RSFQ / Josephson junction
Paper # SCE2000-6
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Conference Information
Committee SCE
Conference Date 2000/4/26(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of a RSFQ Demultiplexer Based on the Shift-and-Dump Architecture
Sub Title (in English)
Keyword(1) demultiplexer
Keyword(2) serial-to-parallel conversion
Keyword(3) RSFQ
Keyword(4) Josephson junction
1st Author's Name Masaaki Maezawa
1st Author's Affiliation Electrotechnical Laboratory()
2nd Author's Name Motohiro Suzuki
2nd Author's Affiliation Electrotechnical Laboratory
3rd Author's Name Akira Shoji
3rd Author's Affiliation Electrotechnical Laboratory
Date 2000/4/26
Paper # SCE2000-6
Volume (vol) vol.100
Number (no) 24
Page pp.pp.-
#Pages 6
Date of Issue