| Presentation | 1994/7/20 A design for a Josephson Built-In Self-Testing(JBIST)system Yoshihito Hashimoto, Shuichi Tahara, Shuichi Nagasawa, Masahiro Aoyagi, Hiroshi Nakagawa, Itaru Kurosawa, Susumu Takada, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have designed a Josephson Built-In Self Testing(JBIST)system for GHz clock tests of Josephson RAMs.The JBIST system consists of the JBIST circuit and a Josephson RAM which is tested by the JBIST circuit.The JBIST circuit consists of a 13 bit x 20 word IROM in which a marching test program is written and an about 300 gates scale processing unit which executes the test program.The total power dissipation of the JBIST system is designed to be 3.69mW.We have made a layout of the JBIST system using an automatic layout technique.From the estimated values of gate delay and propagation delay,GHz clock tests are possible for RAMs with access times of less than 560psec by the JBIST systen,An interface circuit which synchronizes the signals between the JBIST system(GHz)and an external controller(MHz)is indispensable to operate the JBIST system in GHz clock.We have designed an interface circuit and obtained an operating margin of 20% about both bias and input currents by computer simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson device / Memory / Logic circuit / GHz clock testing / Integral circuit / Josephson LSI system |
| Paper # | SCE94-17 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1994/7/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A design for a Josephson Built-In Self-Testing(JBIST)system |
| Sub Title (in English) | |
| Keyword(1) | Josephson device |
| Keyword(2) | Memory |
| Keyword(3) | Logic circuit |
| Keyword(4) | GHz clock testing |
| Keyword(5) | Integral circuit |
| Keyword(6) | Josephson LSI system |
| 1st Author's Name | Yoshihito Hashimoto |
| 1st Author's Affiliation | Fundamental Research Laboratorys,NEC Corporation() |
| 2nd Author's Name | Shuichi Tahara |
| 2nd Author's Affiliation | Fundamental Research Laboratorys,NEC Corporation |
| 3rd Author's Name | Shuichi Nagasawa |
| 3rd Author's Affiliation | Fundamental Research Laboratorys,NEC Corporation |
| 4th Author's Name | Masahiro Aoyagi |
| 4th Author's Affiliation | Electrotechnical Laboratory |
| 5th Author's Name | Hiroshi Nakagawa |
| 5th Author's Affiliation | Electrotechnical Laboratory |
| 6th Author's Name | Itaru Kurosawa |
| 6th Author's Affiliation | Electrotechnical Laboratory |
| 7th Author's Name | Susumu Takada |
| 7th Author's Affiliation | Electrotechnical Laboratory |
| Date | 1994/7/20 |
| Paper # | SCE94-17 |
| Volume (vol) | vol.94 |
| Number (no) | 156 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |