| Presentation | 1998/11/16 Demonstration of 18Gb/s Operation of a Data-Driven Self-Timed RSFQ Demultiplexer N. Yoshikawa, Z.J. Deng, S.R. Whitekey, T.Van Duzer, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a Data-Driven Self-Timed (DDST) Rapid-Single-Flux-Quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10Gb/s operation with sufficient dc bias margin using HYPRES 1kA/cm^2 Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RSFQ circuits / demultiplexer / high speed test / superconducting logic circuits / asynchronous system |
| Paper # | SCE98-36 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1998/11/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Demonstration of 18Gb/s Operation of a Data-Driven Self-Timed RSFQ Demultiplexer |
| Sub Title (in English) | |
| Keyword(1) | RSFQ circuits |
| Keyword(2) | demultiplexer |
| Keyword(3) | high speed test |
| Keyword(4) | superconducting logic circuits |
| Keyword(5) | asynchronous system |
| 1st Author's Name | N. Yoshikawa |
| 1st Author's Affiliation | Faculty of Engineering, Yokohama National University() |
| 2nd Author's Name | Z.J. Deng |
| 2nd Author's Affiliation | IBM T.J.Watson Research Center |
| 3rd Author's Name | S.R. Whitekey |
| 3rd Author's Affiliation | Department of Electrical Engineering and Computer Sciences, University of California |
| 4th Author's Name | T.Van Duzer |
| 4th Author's Affiliation | Department of Electrical Engineering and Computer Sciences, University of California |
| Date | 1998/11/16 |
| Paper # | SCE98-36 |
| Volume (vol) | vol.98 |
| Number (no) | 399 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |