Presentation 1998/11/16
SFQ Logic Circuit using Set/Reset Information
Hiroki Kodaka, Tetsu Hosoki, Manabu Kitagawa, Yoichi OKabe,
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Abstract(in English) We propose a new SFQ data processing method with Set/Reset information in order to clear the defect of synchronization that a pulse coding system like a conventional SFQ circuit has. This method is based on a level coding system like a CMOS circuit and, therefore, it is very easy to design a combinational circuit. In order to realize this method, we propose a new DC/SFQ converter that generates both a set pulse and a reset pulse. The converter is a threshold device and many logic applications are possible. Moreover, we introduce basic logic gates and simulate them.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Level coding logic / Set/Reset pulse / DC/SFQ conversion / Threshold device / Logic device
Paper # SCE98-35
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Committee SCE
Conference Date 1998/11/16(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) SFQ Logic Circuit using Set/Reset Information
Sub Title (in English)
Keyword(1) Level coding logic
Keyword(2) Set/Reset pulse
Keyword(3) DC/SFQ conversion
Keyword(4) Threshold device
Keyword(5) Logic device
1st Author's Name Hiroki Kodaka
1st Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo()
2nd Author's Name Tetsu Hosoki
2nd Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
3rd Author's Name Manabu Kitagawa
3rd Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
4th Author's Name Yoichi OKabe
4th Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
Date 1998/11/16
Paper # SCE98-35
Volume (vol) vol.98
Number (no) 399
Page pp.pp.-
#Pages 6
Date of Issue