| Presentation | 1998/7/28 A Design of Asynchronous Adder Using RSFQ Logic Circuits H. Tago, K. Yoneyama, N. Yoshikawa, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It's difficult to provide synchronous clock signals to every gate in the chip without clock skew in a large scale integrated RSFQ logic circuit operating at very high frequencies.Data-driven self-timed(DDST)system is an asynchronous system, where global clock signals are removed by using complementary signals between the basic cells.We have designed two kinds of 4-bit data-driven self-timed(DDST)RSFQ adder and calculated a circuit yield by taking account of circuit parameter variations due to the fabrication process.The results show that the circuit yield of the DDST adder is larger than that of conventional adder, which represent the validity of the DDST design approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RSFQ / DDST / adder / asynchronous system / circuit yield / dual rail logic |
| Paper # | SCE98-22 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1998/7/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design of Asynchronous Adder Using RSFQ Logic Circuits |
| Sub Title (in English) | |
| Keyword(1) | RSFQ |
| Keyword(2) | DDST |
| Keyword(3) | adder |
| Keyword(4) | asynchronous system |
| Keyword(5) | circuit yield |
| Keyword(6) | dual rail logic |
| 1st Author's Name | H. Tago |
| 1st Author's Affiliation | Faculty of Engineering, Yokohama National University() |
| 2nd Author's Name | K. Yoneyama |
| 2nd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| 3rd Author's Name | N. Yoshikawa |
| 3rd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| Date | 1998/7/28 |
| Paper # | SCE98-22 |
| Volume (vol) | vol.98 |
| Number (no) | 222 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |