| Presentation | 1993/12/8 Estimation of GHz-Clock Operation for Josephson Driver Circuits Yoshihito Hashimoto, Shuichi Nagasawa, Hideaki Numata, Sanae Tsuchida, Shuichi Tahara, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Aiming,at GHz-clock operation for a 4-Kbit Josephson RAM,GHz- clock operation of a resister coupled Josephson polarity- convertible driver circuit which is a key element for the 4-Kbit Josephson RAM GHz-clock operation has been measured and estimated. The driver circuit must do proper polarity-convertible operation and also supply output current enough to drive memory cells.We have done functional tests for the driver circuit.After several improvements on measurement technics,1.3GHz-clock polarity- convertible operation has been observed.Moreover,computer simulations for the driver circuit have been done to estimate the output current quantitatively.We compared the simulated output current of the driver circuit with a measured memory cell operating region.As a result,it has been shown that reductions of load inductances are indispensable for GHz-clock operation of the 4-Kbit RAM.Moreover,we have found that the circulating current in the driven line is hard to eliminate durimg the 1GHz-clock period. This circulating current causes the RAM to operate improperly.To overcome this problem,reset gates for the driver output current are necessary. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson device / Driver circuit / GHz-clock operation / Polarity-convertible driver / Josephson memory |
| Paper # | SCE93-56 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1993/12/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Estimation of GHz-Clock Operation for Josephson Driver Circuits |
| Sub Title (in English) | |
| Keyword(1) | Josephson device |
| Keyword(2) | Driver circuit |
| Keyword(3) | GHz-clock operation |
| Keyword(4) | Polarity-convertible driver |
| Keyword(5) | Josephson memory |
| 1st Author's Name | Yoshihito Hashimoto |
| 1st Author's Affiliation | NEC Fundamental Research Laboratories() |
| 2nd Author's Name | Shuichi Nagasawa |
| 2nd Author's Affiliation | NEC Fundamental Research Laboratories |
| 3rd Author's Name | Hideaki Numata |
| 3rd Author's Affiliation | NEC Fundamental Research Laboratories |
| 4th Author's Name | Sanae Tsuchida |
| 4th Author's Affiliation | NEC Fundamental Research Laboratories |
| 5th Author's Name | Shuichi Tahara |
| 5th Author's Affiliation | NEC Fundamental Research Laboratories |
| Date | 1993/12/8 |
| Paper # | SCE93-56 |
| Volume (vol) | vol.93 |
| Number (no) | 363 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |