Presentation 1993/10/20
A Circuit Design of Josephson Testing LSI for 1GHz Operation
Yoich Hamazaki, Masahiro Aoyagi, Hiroshi Nakagawa, Itaru Kurosawa, Susumu Takada,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A circuit design of Josephson LSI for 1GHz operation testing is described.A multichip module(MCM)for Josephson LSI which provides power distribution of 1GHz AC power and superconductive wiring for interchip connection is under development.The LSI is designed to use with MCM. That LSI contains digital error detecting circuits and it will be able to capture appear-only-once failure.This feature makes possible to demonstrate reliability of Josephson circuits by long time examination without error.Constrain factors like signal propagation delay,the number of pads,etc.are discussed also.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Josephson logic circuit / Operation test circuit / Highspeed circuit design
Paper # SCE93-34
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Conference Information
Committee SCE
Conference Date 1993/10/20(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Circuit Design of Josephson Testing LSI for 1GHz Operation
Sub Title (in English)
Keyword(1) Josephson logic circuit
Keyword(2) Operation test circuit
Keyword(3) Highspeed circuit design
1st Author's Name Yoich Hamazaki
1st Author's Affiliation Electrotechnical Laboratory()
2nd Author's Name Masahiro Aoyagi
2nd Author's Affiliation Electrotechnical Laboratory
3rd Author's Name Hiroshi Nakagawa
3rd Author's Affiliation Electrotechnical Laboratory
4th Author's Name Itaru Kurosawa
4th Author's Affiliation Electrotechnical Laboratory
5th Author's Name Susumu Takada
5th Author's Affiliation Electrotechnical Laboratory
Date 1993/10/20
Paper # SCE93-34
Volume (vol) vol.93
Number (no) 279
Page pp.pp.-
#Pages 6
Date of Issue