Presentation 1993/10/20
Optimization of QFP Majority Logic Circuits
Willy Hioe, Mutsumi Hosoya, Hiroji Yamada, Shinya Kominami,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The problem of increasing the size of QFP majority logic circuits is considered.Previously,in order to achieve a yield of 30% the largest circuit size is limited to 300 QFP′s.If the signal level is increased by reducing the number of input, output lines without worsening parameter fluctuations,an exponential increase in circuit size for the same yield is expected.If the signal current level is 1/5 of the total QFP output current(previously 1/ 8),a 10000-QFP circuit has an expected yield of 90%.The trade-offs are a small increase in delay and more severe wiring constraints. It is shown that a 32-bit fixpoint adder with 32 ps pipeline pitch can achieve a fall-through delay of 176 ps using 3200 QFP′s.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) quantum flux parametron / majority logic / margin / wiring / 32 bit adder
Paper # SCE93-33
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Conference Information
Committee SCE
Conference Date 1993/10/20(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optimization of QFP Majority Logic Circuits
Sub Title (in English)
Keyword(1) quantum flux parametron
Keyword(2) majority logic
Keyword(3) margin
Keyword(4) wiring
Keyword(5) 32 bit adder
1st Author's Name Willy Hioe
1st Author's Affiliation Hitachi()
2nd Author's Name Mutsumi Hosoya
2nd Author's Affiliation Hitachi
3rd Author's Name Hiroji Yamada
3rd Author's Affiliation Hitachi
4th Author's Name Shinya Kominami
4th Author's Affiliation Hitachi
Date 1993/10/20
Paper # SCE93-33
Volume (vol) vol.93
Number (no) 279
Page pp.pp.-
#Pages 6
Date of Issue