| Presentation | 1997/1/22 Technology on Protecting Josephson circuits from Magnetic Flux Trapping and Its Application for Josephson 4-Kbit RAMs Shuichi Nagasawa, Hideaki Numata, Shuichi Tahara, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Moats are designed in different shapes and arranged in different patterns to determine how they affect the I-V characteristics of 1000 serially connected SQUID test circuits. Results show that surrounding the Josephson devices with narrow rectangular moats is very effective in preventing magnetic flux from being trapped, provided that the external magnetic flux within the moats is less than one flux quantum Φ_0. A 4-Kbit RAM, designed with these moats, is operated with an almost full bit yield of 99.8%, without any detrapping. This high bit yield is obtained even with a magnetic field as large as several milli-Gauss. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Magnetic Flux Trapping / Moat / Thermal Current / Josephson Memory / Superconductive IC |
| Paper # | SCE96-30 |
| Date of Issue |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 1997/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Technology on Protecting Josephson circuits from Magnetic Flux Trapping and Its Application for Josephson 4-Kbit RAMs |
| Sub Title (in English) | |
| Keyword(1) | Magnetic Flux Trapping |
| Keyword(2) | Moat |
| Keyword(3) | Thermal Current |
| Keyword(4) | Josephson Memory |
| Keyword(5) | Superconductive IC |
| 1st Author's Name | Shuichi Nagasawa |
| 1st Author's Affiliation | Fundamental Research Labs., NEC Corporation() |
| 2nd Author's Name | Hideaki Numata |
| 2nd Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| 3rd Author's Name | Shuichi Tahara |
| 3rd Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| Date | 1997/1/22 |
| Paper # | SCE96-30 |
| Volume (vol) | vol.96 |
| Number (no) | 452 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |