Presentation 1996/10/30
Design and Operation of Superconductive Interconnection Chip
Shinichi Yorozu, Yoshihito Hashimoto, Shuichi Tahara,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose a superconducting device as a packet switch for processor interconnection. The network architecture is a ring pipeline. This architecture has no contention problems, while conventional multistage networks do have such problems. Therefore, the interface circuit between the processor and network can be designed with less hardware. We report the results of a circuit design and an experimental test for a superconductive switching interface circuit.
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Keyword(in English) superconductivity / superconducting circuits / ring network / processor interconnection / pipelining
Paper # SCE96-19
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Conference Information
Committee SCE
Conference Date 1996/10/30(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Operation of Superconductive Interconnection Chip
Sub Title (in English)
Keyword(1) superconductivity
Keyword(2) superconducting circuits
Keyword(3) ring network
Keyword(4) processor interconnection
Keyword(5) pipelining
1st Author's Name Shinichi Yorozu
1st Author's Affiliation Fundamental Research Laboratories, NEC Corporation()
2nd Author's Name Yoshihito Hashimoto
2nd Author's Affiliation Fundamental Research Laboratories, NEC Corporation
3rd Author's Name Shuichi Tahara
3rd Author's Affiliation Fundamental Research Laboratories, NEC Corporation
Date 1996/10/30
Paper # SCE96-19
Volume (vol) vol.96
Number (no) 333
Page pp.pp.-
#Pages 6
Date of Issue