Presentation 1995/7/26
Implementation of DC-Biased Coupled-SQUID Gates into an RS Flip-Flop
Yoshinao Mizugaki, Koji Nakajima, Tsutomu Yamashita,
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Abstract(in English) We present the experimental implementation of dc-biased coupled-SQUID (C-SQUID) gates into an RS flip-flop (RS-FF). The C-SQUID gate is a combinaion of a single junction SQUID and a double-junction SQUID. This gate utilizes non-hysteretic Josephson junctions and is operated in non-latching mode with dc-biasing. Several logical functions can be realized with the C-SQUID gate by adjusting the input bias and input signal levels. The RS-FF is composed of two C-SQUID NOR gates. First, the performance of the single gate and the RS-FF was evaluated by simulation. Next, we fabricated the RS-FF using a Nb/AlO_x/Nb junction technology and demonstrated its operation experimentally.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) dc-biased Josephson device / logic circuit / coupled-SQUID / flip-flop / Nb/AlO_x/Nb junction
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Committee SCE
Conference Date 1995/7/26(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of DC-Biased Coupled-SQUID Gates into an RS Flip-Flop
Sub Title (in English)
Keyword(1) dc-biased Josephson device
Keyword(2) logic circuit
Keyword(3) coupled-SQUID
Keyword(4) flip-flop
Keyword(5) Nb/AlO_x/Nb junction
1st Author's Name Yoshinao Mizugaki
1st Author's Affiliation Research Institute of Electrical Communication, Tohoku University()
2nd Author's Name Koji Nakajima
2nd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
3rd Author's Name Tsutomu Yamashita
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
Date 1995/7/26
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Volume (vol) vol.95
Number (no) 186
Page pp.pp.-
#Pages 6
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