Presentation 1998/1/28
Design of Signed Ternary Logic Circuit Using dc-SQUIDs
Katsuya Kikuchi, Susumu Takada, Mititada Morisue,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) 1x1-trit Josephson multiplier and half adder circuits have been designed based on signed ternary (ST) logic operation using dc-SQUIDs. It has been shown that a full adder and 2x2-trit multiplier are constructed by connecting the basic ternary gates in multi-stage logic circuits. The logic operation of these circuits and logic speed were investigated by logic simulator. The logic speed was 30ps/gate. The fan-out of more than 2 was obtained for multi-stage connection. It has been found that for multi-stage logic circuits a multi-phase power is required. It has been shown that 2x2-trit Josephson multiplier is consisting of 6-stage logic circuits and the logic speed is 180ps.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) dc-SQUID / signed ternary / Josephson adder / Josephson multiplier
Paper # SCE97-38
Date of Issue

Conference Information
Committee SCE
Conference Date 1998/1/28(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Signed Ternary Logic Circuit Using dc-SQUIDs
Sub Title (in English)
Keyword(1) dc-SQUID
Keyword(2) signed ternary
Keyword(3) Josephson adder
Keyword(4) Josephson multiplier
1st Author's Name Katsuya Kikuchi
1st Author's Affiliation Faculty of Engineering, Saitama University()
2nd Author's Name Susumu Takada
2nd Author's Affiliation Faculty of Engineering, Saitama University
3rd Author's Name Mititada Morisue
3rd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
Date 1998/1/28
Paper # SCE97-38
Volume (vol) vol.97
Number (no) 516
Page pp.pp.-
#Pages 6
Date of Issue