| Presentation | 1997/11/20 Dual-rail RSFQ shift register on delay-insensitive model and its applications Masaaki Maezawa, Stas Polonsky, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present new implementation of dual-rail RSFQ shift registers on the delay-insensitive (DI) model. The shift register consists of a series of destructive read out cells designed on DI model and employs a hand shaking protocol. PSCAN simulation estimates throughput of a FIFO mode of the DI shift register to be 10 Gbps for 1-kA/cm^2 Nb technology. Some DI circuits based on the shift resisters, a micropipeline processor, serial-to-parallel and parallel-to-serial converters, Me designed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | delay-insensitive model / RSFQ / shift register / pipeline |
| Paper # | SCE97-29 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1997/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dual-rail RSFQ shift register on delay-insensitive model and its applications |
| Sub Title (in English) | |
| Keyword(1) | delay-insensitive model |
| Keyword(2) | RSFQ |
| Keyword(3) | shift register |
| Keyword(4) | pipeline |
| 1st Author's Name | Masaaki Maezawa |
| 1st Author's Affiliation | Electrotechnical Laboratory() |
| 2nd Author's Name | Stas Polonsky |
| 2nd Author's Affiliation | SUNY Stony Brook |
| Date | 1997/11/20 |
| Paper # | SCE97-29 |
| Volume (vol) | vol.97 |
| Number (no) | 383 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |