| Presentation | 1997/11/20 High-speed Testing of Josephson Logic Circuits with an On-chip Signal-pattern Generator Y. Hashimoto, S. Yorozu, H. Numata, M. Koike, M. Tanaka, S. Tahara, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage D flip-flop is fed back to the first-stage D flip-flop. Since the SPG consists of only D flip-flops and requires no external control signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a clock frequency of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson Device / Josephson IC / High-speed Testing |
| Paper # | SCE97-26 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1997/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-speed Testing of Josephson Logic Circuits with an On-chip Signal-pattern Generator |
| Sub Title (in English) | |
| Keyword(1) | Josephson Device |
| Keyword(2) | Josephson IC |
| Keyword(3) | High-speed Testing |
| 1st Author's Name | Y. Hashimoto |
| 1st Author's Affiliation | Fundamental Research Labs., NEC Corporation() |
| 2nd Author's Name | S. Yorozu |
| 2nd Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| 3rd Author's Name | H. Numata |
| 3rd Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| 4th Author's Name | M. Koike |
| 4th Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| 5th Author's Name | M. Tanaka |
| 5th Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| 6th Author's Name | S. Tahara |
| 6th Author's Affiliation | Fundamental Research Labs., NEC Corporation |
| Date | 1997/11/20 |
| Paper # | SCE97-26 |
| Volume (vol) | vol.97 |
| Number (no) | 383 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |