Presentation 1999/7/16
Moment Extraction Architecture for Digital Vision Chip
Takashi Komuro, Idaku Ishii, Yoshihiro Nakabo, Masatoshi Ishikawa,
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Abstract(in English) A vision chip in which photo detectors (PD) and processing elements (PE) are directly connected in each pixel and are integrated on a single chip solves the bottleneck problem at the input stage but the bottleneck at the output stage still exists. To solve the problem, in this paper, we propose an architecture for extracting moments as outputs especially targetting vision chips consisting of digital circuits. Also we present some examples of moments calcuration and evaluate the architecture at the point of speed and implementation.
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Keyword(in English) vision chip / visual feedback / I/O bottleneck / moment / VLSI
Paper # PRMU99-51
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Conference Information
Committee PRMU
Conference Date 1999/7/16(1days)
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Registration To Pattern Recognition and Media Understanding (PRMU)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Moment Extraction Architecture for Digital Vision Chip
Sub Title (in English)
Keyword(1) vision chip
Keyword(2) visual feedback
Keyword(3) I/O bottleneck
Keyword(4) moment
Keyword(5) VLSI
1st Author's Name Takashi Komuro
1st Author's Affiliation Department of Mathematical Engineering and Information Physics, School of Engineering, Univ. of Tokyo()
2nd Author's Name Idaku Ishii
2nd Author's Affiliation Department of Mathematical Engineering and Information Physics, School of Engineering, Univ. of Tokyo
3rd Author's Name Yoshihiro Nakabo
3rd Author's Affiliation Department of Mathematical Engineering and Information Physics, School of Engineering, Univ. of Tokyo
4th Author's Name Masatoshi Ishikawa
4th Author's Affiliation Department of Mathematical Engineering and Information Physics, School of Engineering, Univ. of Tokyo
Date 1999/7/16
Paper # PRMU99-51
Volume (vol) vol.99
Number (no) 182
Page pp.pp.-
#Pages 6
Date of Issue