| Presentation | 1998/7/24 A Study on the Video Scalability Rate Control Method by Dynamic Controlling of Bits Allocation Ratio Hiroyuki KASAI, Mei KODAMA, Hideyoshi TOMINAGA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we study the analysis of the video quality according to the coding bits allocation to the base-layer and enhancement-layer, and the video scalability coding rate control method considering the relation video image and allocated bits. In particular, we use the MPEG-2 SNR Scalability. First of all, we investigate the efficiency of SNR scalability from simulation experiments, and we define the characteristic function. Next we propose the coding rate control method from this characteristc. From the simulation experiment, we show the effivtiveness in comparison to TM5 rate control method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hierarchical Allocated Bits / Rate Control / SNR Scalability / TM5 |
| Paper # | IE98-35,PRMU98-58,MVE98-58 |
| Date of Issue |
| Conference Information | |
| Committee | PRMU |
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| Conference Date | 1998/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Pattern Recognition and Media Understanding (PRMU) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on the Video Scalability Rate Control Method by Dynamic Controlling of Bits Allocation Ratio |
| Sub Title (in English) | |
| Keyword(1) | Hierarchical Allocated Bits |
| Keyword(2) | Rate Control |
| Keyword(3) | SNR Scalability |
| Keyword(4) | TM5 |
| 1st Author's Name | Hiroyuki KASAI |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, WASEDA University() |
| 2nd Author's Name | Mei KODAMA |
| 2nd Author's Affiliation | Center for Technology Research & Development, Hiroshima University |
| 3rd Author's Name | Hideyoshi TOMINAGA |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, WASEDA University |
| Date | 1998/7/24 |
| Paper # | IE98-35,PRMU98-58,MVE98-58 |
| Volume (vol) | vol.98 |
| Number (no) | 206 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |