Presentation | 1997/5/15 2-Level Brainware Architecture for Traffic System Tadashi Ae, Keiichi Sakai, Hiroyuki Araki, Ken-Ichi Katakawa, Saku Hiwatashi, Satoshi Kaneko, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A two-level Brainware architecture consisting of Component Level (for elementary pattern recognition) and Structure Level (for syntax pattern recognition) has been proposed. We state this architecture and how to use it for recognition of time-axis structure. We investigate this architecture to be applied for traffic system. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | real-time processing / image understanding / neural network / two-level architecture |
Paper # | PRMU97-11 |
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Committee | PRMU |
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Conference Date | 1997/5/15(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Pattern Recognition and Media Understanding (PRMU) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | 2-Level Brainware Architecture for Traffic System |
Sub Title (in English) | |
Keyword(1) | real-time processing |
Keyword(2) | image understanding |
Keyword(3) | neural network |
Keyword(4) | two-level architecture |
1st Author's Name | Tadashi Ae |
1st Author's Affiliation | Electrical Engineering, Faculty of Engineering, Hiroshima University() |
2nd Author's Name | Keiichi Sakai |
2nd Author's Affiliation | Electrical Engineering, Faculty of Engineering, Hiroshima University |
3rd Author's Name | Hiroyuki Araki |
3rd Author's Affiliation | Electrical Engineering, Faculty of Engineering, Hiroshima University |
4th Author's Name | Ken-Ichi Katakawa |
4th Author's Affiliation | Electrical Engineering, Faculty of Engineering, Hiroshima University |
5th Author's Name | Saku Hiwatashi |
5th Author's Affiliation | Electrical Engineering, Faculty of Engineering, Hiroshima University |
6th Author's Name | Satoshi Kaneko |
6th Author's Affiliation | Electrical Engineering, Faculty of Engineering, Hiroshima University |
Date | 1997/5/15 |
Paper # | PRMU97-11 |
Volume (vol) | vol.97 |
Number (no) | 40 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |