| Presentation | 1997/9/24 Implementation of 2Mbps Adaptive MLSE using FPGA Keiichi KITAGAWA, Akihiro OKAZAKI, Hidekazu MURATA, Susumu YOSHIDA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In order to realize high speed transmission in digital mobile communications, the design trials of equalizer are being investigated actively. Adaptive equalizer which uses path diversity has been proved to be an effective method against multipath propagation causing frequency selective fading in high speed transmission. The MLSE is well-known to yield a superior path diversity effect, but the computational complexity increases rapidly when the multipath delay becomes large. In this paper, by reducing the computational bits in the circuit, and simplifying the calculation complexity without sacrificing the performance, we successfully designed a small-scale, high speed adaptive MLSE equalizer. This edualizer is realized on a FPGA circuit. Its operation and processing speed (2Mbps) have been confirmed to be consistent with the design goal. It is further extended to realize the Trellis-coded Co-channel Interference Canceller. The operation of the canceller is confirmed and its performance is studied. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | mobile communication / high speed transmission / adaptive equalizer / programmable logic device / computational complexity reduction / interference canceller |
| Paper # | RCS97-83 |
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| Conference Information | |
| Committee | RCS |
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| Conference Date | 1997/9/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Radio Communication Systems (RCS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of 2Mbps Adaptive MLSE using FPGA |
| Sub Title (in English) | |
| Keyword(1) | mobile communication |
| Keyword(2) | high speed transmission |
| Keyword(3) | adaptive equalizer |
| Keyword(4) | programmable logic device |
| Keyword(5) | computational complexity reduction |
| Keyword(6) | interference canceller |
| 1st Author's Name | Keiichi KITAGAWA |
| 1st Author's Affiliation | Faculty of Engineering, Kyoto University() |
| 2nd Author's Name | Akihiro OKAZAKI |
| 2nd Author's Affiliation | Faculty of Engineering, Kyoto University |
| 3rd Author's Name | Hidekazu MURATA |
| 3rd Author's Affiliation | Faculty of Engineering, Kyoto University |
| 4th Author's Name | Susumu YOSHIDA |
| 4th Author's Affiliation | Faculty of Engineering, Kyoto University |
| Date | 1997/9/24 |
| Paper # | RCS97-83 |
| Volume (vol) | vol.97 |
| Number (no) | 266 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |