Presentation 1997/7/25
Third-Order Phase-Locked Loops using Dual Loops with Improved Stability
Minoru Kamata, Takashi Shono, Takahiko Saba, Shinsaku Mori,
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Abstract(in English) In satellite communications, phase-locked loops (PLLs) must track a input signal which has not only frequency step transition, but also frequency ramp transition. A second-order PLL cannot suppress the steady-state phase error in such an environment. A third-order PLL is required to suppress steady-state error. However, the third-order PLL is a problem that is an instability. In this study, we propose the new third-order PLL using dual loops. We investigate the transient response and the steady-state behavior of the PLL due to the frequency ramp transition. Results show the steady-state error of the proposed PLL is suppressed. Furthermore, we show the stability of the proposed PLL is improved.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) PLL / frequency ramp transition / the steady-state phase error / stability
Paper # RCS97-72
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Committee RCS
Conference Date 1997/7/25(1days)
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Registration To Radio Communication Systems (RCS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Third-Order Phase-Locked Loops using Dual Loops with Improved Stability
Sub Title (in English)
Keyword(1) PLL
Keyword(2) frequency ramp transition
Keyword(3) the steady-state phase error
Keyword(4) stability
1st Author's Name Minoru Kamata
1st Author's Affiliation Dept. of Electrical Engineering, Keio University()
2nd Author's Name Takashi Shono
2nd Author's Affiliation Dept. of Electrical Engineering, Keio University
3rd Author's Name Takahiko Saba
3rd Author's Affiliation Dept. of Electrical and Computer Engineering, Nagoya Institute of Technology
4th Author's Name Shinsaku Mori
4th Author's Affiliation Dept.of Electrical and Electronics Engineering, Nippon Institute of Technology
Date 1997/7/25
Paper # RCS97-72
Volume (vol) vol.97
Number (no) 194
Page pp.pp.-
#Pages 6
Date of Issue