| Presentation | 2001/9/10 On the criteria of hardware evaluation of block ciphers(2) Toru SORIMACHI, Tetsuya ICHIKAWA, Tomomi KASUYA, Mitsuru MATSUI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In"On the criteria of hardware evaluation of block ciphers(1)", we proposed a new method for estimating effectiveness of hardware implementation, that is, "Throughput/{Area^* Latency}". In this report, we describe implementation results of hardware of MISTY1 on Field Programmable Gate Arrays(FPGAs), using Vertex-E family(XCV1000EBG560-8, XCV3200ECG1156-8)which is a product of Xilinx, Inc. This report also describes comparison results of implementing hardware of MISTY1 with other cipher algorithms that has already been reported. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cipher / block cipher / MISTY1 / hardware / FPGA |
| Paper # | ISEC 2001-54 |
| Date of Issue |
| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2001/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the criteria of hardware evaluation of block ciphers(2) |
| Sub Title (in English) | |
| Keyword(1) | cipher |
| Keyword(2) | block cipher |
| Keyword(3) | MISTY1 |
| Keyword(4) | hardware |
| Keyword(5) | FPGA |
| 1st Author's Name | Toru SORIMACHI |
| 1st Author's Affiliation | Mitsubishi Electric corporation Information Technology R&D Center() |
| 2nd Author's Name | Tetsuya ICHIKAWA |
| 2nd Author's Affiliation | Mitsubishi Electric corporation Information Technology R&D Center |
| 3rd Author's Name | Tomomi KASUYA |
| 3rd Author's Affiliation | Mitsubishi Electric corporation Information Technology R&D Center |
| 4th Author's Name | Mitsuru MATSUI |
| 4th Author's Affiliation | Mitsubishi Electric corporation Information Technology R&D Center |
| Date | 2001/9/10 |
| Paper # | ISEC 2001-54 |
| Volume (vol) | vol.101 |
| Number (no) | 311 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |