Presentation 2001/9/10
On the criteria of hardware evaluation of block ciphers(1)
Tetsuya ICHIKAWA, Toru SORIMACHI, Tomomi KASUYA, Mitsuru MATSUI,
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Abstract(in English) This report proposes a new parameter for estimating the effectiveness of hardware implementation. We point out a problem of existing parameters for hardware estimation and introduce a new index, "Throughput/(Area^* Latency)". This report also describes our results of implementing Camellia and reduced Camellia hardware on Field Programmable Gate Array(FPGA), using Virtex-E family(XCV1000E-8-FG1156)which is a product of Xilinx, Inc.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) cipher / block cipher / Camellia / hardware / FPGA
Paper # ISEC 2001-53
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Committee ISEC
Conference Date 2001/9/10(1days)
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Paper Information
Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On the criteria of hardware evaluation of block ciphers(1)
Sub Title (in English)
Keyword(1) cipher
Keyword(2) block cipher
Keyword(3) Camellia
Keyword(4) hardware
Keyword(5) FPGA
1st Author's Name Tetsuya ICHIKAWA
1st Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center()
2nd Author's Name Toru SORIMACHI
2nd Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
3rd Author's Name Tomomi KASUYA
3rd Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
4th Author's Name Mitsuru MATSUI
4th Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
Date 2001/9/10
Paper # ISEC 2001-53
Volume (vol) vol.101
Number (no) 311
Page pp.pp.-
#Pages 8
Date of Issue