Presentation 2001/7/18
AES hardware implementation for smart cards
Souichi OKADA, Naoya TORII, Takayuki HASEBE,
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Abstract(in English) We describe a hardware implementation of AES(Rijndael)for smart cards.We show the hardware configuration, the result of the FPGA implementation and the performance evaluation of the ASIC implementation using 0.35μm CMOS ASIC.The hardware encrypts/decrypts the data with 128 bit, 192 bit, and 256 bit key.And it supports CBC mode of operation.In the FPGA implementation by ALTERA EP1K100QC208-3, the throughput is 44 Mbps at 32 MHz when key length is 128 bit.In the ASIC implementation, the hardware size is 17.6 Kgates, and the throughput is 73 Mbps when key length is 128 implementation, the hardware size is 17.6 Kgates, and the throughput is 73 Mbps when key length is 128 bit.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Block cipher / AES / Rijndael / FPGA
Paper # ISEC2001-34
Date of Issue

Conference Information
Committee ISEC
Conference Date 2001/7/18(1days)
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Paper Information
Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) AES hardware implementation for smart cards
Sub Title (in English)
Keyword(1) Block cipher
Keyword(2) AES
Keyword(3) Rijndael
Keyword(4) FPGA
1st Author's Name Souichi OKADA
1st Author's Affiliation FUJITSU LABORATORIES LTD()
2nd Author's Name Naoya TORII
2nd Author's Affiliation FUJITSU LABORATORIES LTD
3rd Author's Name Takayuki HASEBE
3rd Author's Affiliation FUJITSU LABORATORIES LTD
Date 2001/7/18
Paper # ISEC2001-34
Volume (vol) vol.101
Number (no) 214
Page pp.pp.-
#Pages 8
Date of Issue