Presentation 1993/10/25
A High-speed Modular Multiplication Method for the RSA Cryptosystem
Jungtae Kim, Hongsub Lee, Daiki Lee,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper describes the architecture and design of a multiplier for a public key encryption and decryption processor which implements the RSA algorithm with key lengths of 512 bits.The algorithm is based on the parallel multiplier to achieve the necessary throughput.The multiplier has been designed by a 0.8 micron CMOS gate array process and implemented with 71,680 transistors.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Cryptography / Key Distribution / Key Sharing / Identifier / IC Cards / Information Security
Paper # ISEC93-41
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Conference Information
Committee ISEC
Conference Date 1993/10/25(1days)
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Paper Information
Registration To Information Security (ISEC)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A High-speed Modular Multiplication Method for the RSA Cryptosystem
Sub Title (in English)
Keyword(1) Cryptography
Keyword(2) Key Distribution
Keyword(3) Key Sharing
Keyword(4) Identifier
Keyword(5) IC Cards
Keyword(6) Information Security
1st Author's Name Jungtae Kim
1st Author's Affiliation Electronics & Telecommunications Research Institute()
2nd Author's Name Hongsub Lee
2nd Author's Affiliation Electronics & Telecommunications Research Institute
3rd Author's Name Daiki Lee
3rd Author's Affiliation Electronics & Telecommunications Research Institute
Date 1993/10/25
Paper # ISEC93-41
Volume (vol) vol.93
Number (no) 295
Page pp.pp.-
#Pages 6
Date of Issue