Presentation 1997/3/18
Si CMOS Digital Matched Filter(DMF) : Design and Fabricate of 0.8μm DMF and performance evaluation of 0.2μm DMF
Y. Fujita, K. Masu, K. Tsubouchi,
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Abstract(in English) We designed and fabricated Digital Matched Filter (DMF) using 0.8μm CMOS Technology ; Code type is 128-chip orthogonal m-sequence. Total number of MOSFET is 60,970; The numbers of MOSFET in the delay line block and adder block are 21,504 and 39,466, respectively. The maximum operation frequency was 10.2MHz@5V and the consumption power was 294mW@5V, 10MHz. Using the performance of 0.8μm CMOS DMF, the performance of 0.2μm CMOS DMF has been estimated ; The maximum clock frequency and the power areb evaluated to be 100MHz@1.8V and 180mW@1.8V, 100MHz, respectively.
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Keyword(in English) Matched Filter / Si process / Digital Matched Filter
Paper # IT96-64,ISEC96-56,SST96-71
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Committee ISEC
Conference Date 1997/3/18(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Si CMOS Digital Matched Filter(DMF) : Design and Fabricate of 0.8μm DMF and performance evaluation of 0.2μm DMF
Sub Title (in English)
Keyword(1) Matched Filter
Keyword(2) Si process
Keyword(3) Digital Matched Filter
1st Author's Name Y. Fujita
1st Author's Affiliation Research Institute of Electrical Communication, Tohoku University()
2nd Author's Name K. Masu
2nd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
3rd Author's Name K. Tsubouchi
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
Date 1997/3/18
Paper # IT96-64,ISEC96-56,SST96-71
Volume (vol) vol.96
Number (no) 588
Page pp.pp.-
#Pages 6
Date of Issue