Presentation 1995/10/23
Post-annealing Effects on the Characteristics of Poly-Si TFT's
Kwon-Young Choi, Yong-Sang Kim, Min-Koo Han,
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Abstract(in English) The amorphous silicon films deposited by low pressure chemical vapor deposition are crystallized by the various annealing techniques including low-temperature furnace annealing, excimer laser annealing and two-step annealing. Two-step annealing, which is the combination of furnace annealing at 600 ℃ for 24 h and the sequential furnace annealing at 950℃/1h or the excimer laser annealing, is found to reduce the in-grain defects significantly without changing the grain boundary structure. As a consequence, the performance of the poly-Si thin film transistors (TFT's) produced by employing the two-step annealing has been improved remarkably if compared with those of one-step annealing.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Poly-Si Thin Film Transistors / Two-step Annealing / Grain Boundary / In-grain Defects
Paper # EID95-44
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Committee EID
Conference Date 1995/10/23(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Post-annealing Effects on the Characteristics of Poly-Si TFT's
Sub Title (in English)
Keyword(1) Poly-Si Thin Film Transistors
Keyword(2) Two-step Annealing
Keyword(3) Grain Boundary
Keyword(4) In-grain Defects
1st Author's Name Kwon-Young Choi
1st Author's Affiliation Dep't. of Electrical Eng., Seoul National University()
2nd Author's Name Yong-Sang Kim
2nd Author's Affiliation Dep't. of Electrical Eng., Myongji University
3rd Author's Name Min-Koo Han
3rd Author's Affiliation Dep't. of Electrical Eng., Seoul National University
Date 1995/10/23
Paper # EID95-44
Volume (vol) vol.95
Number (no) 335
Page pp.pp.-
#Pages 6
Date of Issue