Presentation | 1996/10/31 A Reset Circuitry for the Differential Amplifier with Floating Gate Transistors Takeyasu Sakai, Hiromasa Nagai, Takashi Matsumoto, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A reset circuitry is proposed for compensating various offset effects in the multi-input floating gate differential amplifier (FGDA). The latter is a basic building block for intelligent image sensors proposed by the present authors in a previous paper. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | intelligent sensor / image compression / DCT / vision chip / floating gate |
Paper # | EID96-48 |
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Conference Information | |
Committee | EID |
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Conference Date | 1996/10/31(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
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Assistant |
Paper Information | |
Registration To | Electronic Information Displays (EID) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Reset Circuitry for the Differential Amplifier with Floating Gate Transistors |
Sub Title (in English) | |
Keyword(1) | intelligent sensor |
Keyword(2) | image compression |
Keyword(3) | DCT |
Keyword(4) | vision chip |
Keyword(5) | floating gate |
1st Author's Name | Takeyasu Sakai |
1st Author's Affiliation | Electronic Navigation Research Institute, Ministry of Transport() |
2nd Author's Name | Hiromasa Nagai |
2nd Author's Affiliation | Department of Electrical, Electronics and Computer Engineering, Waseda University |
3rd Author's Name | Takashi Matsumoto |
3rd Author's Affiliation | Department of Electrical, Electronics and Computer Engineering, Waseda University |
Date | 1996/10/31 |
Paper # | EID96-48 |
Volume (vol) | vol.96 |
Number (no) | 340 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |