Presentation 1996/10/31
A Reset Circuitry for the Differential Amplifier with Floating Gate Transistors
Takeyasu Sakai, Hiromasa Nagai, Takashi Matsumoto,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) A reset circuitry is proposed for compensating various offset effects in the multi-input floating gate differential amplifier (FGDA). The latter is a basic building block for intelligent image sensors proposed by the present authors in a previous paper.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) intelligent sensor / image compression / DCT / vision chip / floating gate
Paper # EID96-48
Date of Issue

Conference Information
Committee EID
Conference Date 1996/10/31(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Electronic Information Displays (EID)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Reset Circuitry for the Differential Amplifier with Floating Gate Transistors
Sub Title (in English)
Keyword(1) intelligent sensor
Keyword(2) image compression
Keyword(3) DCT
Keyword(4) vision chip
Keyword(5) floating gate
1st Author's Name Takeyasu Sakai
1st Author's Affiliation Electronic Navigation Research Institute, Ministry of Transport()
2nd Author's Name Hiromasa Nagai
2nd Author's Affiliation Department of Electrical, Electronics and Computer Engineering, Waseda University
3rd Author's Name Takashi Matsumoto
3rd Author's Affiliation Department of Electrical, Electronics and Computer Engineering, Waseda University
Date 1996/10/31
Paper # EID96-48
Volume (vol) vol.96
Number (no) 340
Page pp.pp.-
#Pages 6
Date of Issue