Presentation 2000/3/10
A Study on High Performance Processor Architecture in large capacity Node Systems
Masaki YAMAMOTO, Takeshi MISHIMA, Michihiri AOKI,
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Abstract(in English) To realize large capacity node systems, high performance processor architecture in node systems is needed. In addition, highly reliable and cost efective processor architecture must be established. In this papaer, we estimate reliability and costwise of high performance processor architectures, and describe construction method of them. Furthermore, we estimate multiprocessor reduancy architecture to be achieved highly reliable and cost-efficent design in node systems.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) large capacity node systems / hight performance processor / multiprocessor / fault tolerant systems / unavailability depending on failure magnitude / redundancy
Paper # SSE99-197,IN99-160
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Committee SSE
Conference Date 2000/3/10(1days)
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Registration To Switching Systems Engineering (SSE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Study on High Performance Processor Architecture in large capacity Node Systems
Sub Title (in English)
Keyword(1) large capacity node systems
Keyword(2) hight performance processor
Keyword(3) multiprocessor
Keyword(4) fault tolerant systems
Keyword(5) unavailability depending on failure magnitude
Keyword(6) redundancy
1st Author's Name Masaki YAMAMOTO
1st Author's Affiliation NTT Network Service Systems Laboratories()
2nd Author's Name Takeshi MISHIMA
2nd Author's Affiliation NTT Network Service Systems Laboratories
3rd Author's Name Michihiri AOKI
3rd Author's Affiliation NTT Network Service Systems Laboratories
Date 2000/3/10
Paper # SSE99-197,IN99-160
Volume (vol) vol.99
Number (no) 675
Page pp.pp.-
#Pages 6
Date of Issue