| Presentation | 1995/7/14 Design Technique of Fault-tolerant Multistage Interconnection Networks for ATM Switching Networks Takashi Shimizu, Toshiyuki Iino, Hiroaki Kunieda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | ATM switching and transmission systems is promising, because they can provide us multimedia communication services, by which we can exchange voice, high-speed data, and high resolution images. Therefore, how to implement the systems is one of the important issue for realizing the B-ISDN as a future infrastructure. In ATM switching networks, each switch along the route of ATM cells has only to route them independently according to their header. This scheme is called self-routing. If the network has redundancy of routes between an input and an output, the ATM cells can avoid failed switches only by changing their routin tag, even if several ATM switches which forms the network have failed. Therefore, this scheme reveals the possibility to design the ATM switching networks as gracefully degrading systems. This paper presents a design technique of fault-tolerant multistage interconnection networks for the ATM switching networks. We present the augmented multistage interconnection network with expanded middle stages, and show it become a gracefully degrading system. Simulation shows that the network Can keep required performance even when several switches in the network have failed. We also show that the optimum configuration is the proposed networks whose addition stages α=1 and expansion ratio γ=3/2 when network size N≥2^4. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous Transfer Mode / Multistage Interconnection Network / Fault Tolerant / Gracefully Degrading System / Throughput / Cell Loss Probability / Cell Delay |
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| Conference Information | |
| Committee | SSE |
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| Conference Date | 1995/7/14(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Switching Systems Engineering (SSE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Technique of Fault-tolerant Multistage Interconnection Networks for ATM Switching Networks |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous Transfer Mode |
| Keyword(2) | Multistage Interconnection Network |
| Keyword(3) | Fault Tolerant |
| Keyword(4) | Gracefully Degrading System |
| Keyword(5) | Throughput |
| Keyword(6) | Cell Loss Probability |
| Keyword(7) | Cell Delay |
| 1st Author's Name | Takashi Shimizu |
| 1st Author's Affiliation | Tokyo Institute of Technology() |
| 2nd Author's Name | Toshiyuki Iino |
| 2nd Author's Affiliation | Fujitsu Limited |
| 3rd Author's Name | Hiroaki Kunieda |
| 3rd Author's Affiliation | Tokyo Institute of Technology |
| Date | 1995/7/14 |
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| Volume (vol) | vol.95 |
| Number (no) | 142 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |