Presentation 1996/6/18
Design of Si-OEIC using Lateral pin-PD
Takayuki Koyama, Shin-ichi Murai, Masahiro Tsuchiya, Takeshi Kamiya,
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Abstract(in English) We have designed a lateral pin-PD, which can be fabricated by conventional CMOS processing technology. Using 0.5μm CMOS fabrication process combined with the lateral pin-PD we have designed a Si-OEIC. Simulations showed that we could achieved maximum transfer speeds of 450Mb/s and 350Mb/s for CMOS and nMOS, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) OEIC / CMOS / nMOS / pin-PD / 0.5μmCMOS process technology
Paper # LQE96-20
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Conference Information
Committee LQE
Conference Date 1996/6/18(1days)
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Registration To Lasers and Quantum Electronics (LQE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Si-OEIC using Lateral pin-PD
Sub Title (in English)
Keyword(1) OEIC
Keyword(2) CMOS
Keyword(3) nMOS
Keyword(4) pin-PD
Keyword(5) 0.5μmCMOS process technology
1st Author's Name Takayuki Koyama
1st Author's Affiliation Department of Electronics Engineering, Faculty of Engineering, Tokyo University()
2nd Author's Name Shin-ichi Murai
2nd Author's Affiliation Department of Electronics Engineering, Faculty of Engineering Tokyo University
3rd Author's Name Masahiro Tsuchiya
3rd Author's Affiliation Department of Electronics Engineering, Faculty of Engineering Tokyo University
4th Author's Name Takeshi Kamiya
4th Author's Affiliation Department of Electronics Engineering, Faculty of Engineering Tokyo University
Date 1996/6/18
Paper # LQE96-20
Volume (vol) vol.96
Number (no) 98
Page pp.pp.-
#Pages 6
Date of Issue