Presentation 1997/7/25
V-Band Low Noise HMIC Amplifier with an Impedance Inverter Including FET's Parasitic Reactances
Hiromitsu Uchida, Hideshi Hanjyo, Yasushi Itoh,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This report describes the design, fabrication and performance of a millimeter-wave low-noise HMIC amplifier with band-pass filters including FET's parasitic reactances. The amplifier is useful at the high frequency where FET has considerably large reactance, and has a feature that a miniaturized size can be achieved by employing a coupled line for d.c. blocking.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) millmeter-wave / HMIC / parasitic reactances / coupled line
Paper # CQ97-32
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Conference Information
Committee CQ
Conference Date 1997/7/25(1days)
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Paper Information
Registration To Communication Quality (CQ)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) V-Band Low Noise HMIC Amplifier with an Impedance Inverter Including FET's Parasitic Reactances
Sub Title (in English)
Keyword(1) millmeter-wave
Keyword(2) HMIC
Keyword(3) parasitic reactances
Keyword(4) coupled line
1st Author's Name Hiromitsu Uchida
1st Author's Affiliation Mitsubishi Electric Corporation()
2nd Author's Name Hideshi Hanjyo
2nd Author's Affiliation Mitsubishi Electric Corporation
3rd Author's Name Yasushi Itoh
3rd Author's Affiliation Mitsubishi Electric Corporation
Date 1997/7/25
Paper # CQ97-32
Volume (vol) vol.97
Number (no) 190
Page pp.pp.-
#Pages 6
Date of Issue