Presentation 1997/7/24
A Consideration on the Coding Efficiency of Video Scalability from Hierarchical Bit Allocation
Hiroyuki KASAI, Mei KODAMA, Hideyoshi TOMINAGA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper aims at the coding characteristic analysis of video scalability from changes by bit allocation to each layers from simulation experiment. In SNR scalability, on sequences which have less motions, hierarchical loss has an influence on enhancement layer quality Otherwise, on sequences which have more motions, hierarchical loss and temporal coding loess have an great influence on enhancement layer quality. In spatial scalability, according to the increase of coding bit allocation ratio, enhancement layer quality decrease. Moreover, according to the increase of coding bit allocation ratio, spatial prediction has more influence on enhancement layer quality.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SNR Scalability / Spatial Scalability / Bit Allocation / Coding Characteristics
Paper # MVE97-52
Date of Issue

Conference Information
Committee MVE
Conference Date 1997/7/24(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Media Experience and Virtual Environment (MVE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Consideration on the Coding Efficiency of Video Scalability from Hierarchical Bit Allocation
Sub Title (in English)
Keyword(1) SNR Scalability
Keyword(2) Spatial Scalability
Keyword(3) Bit Allocation
Keyword(4) Coding Characteristics
1st Author's Name Hiroyuki KASAI
1st Author's Affiliation Dept. of Electronics, Information and Communication Engineering, WASEDA University()
2nd Author's Name Mei KODAMA
2nd Author's Affiliation Dept. of Electronics, Information and Communication Engineering, WASEDA University
3rd Author's Name Hideyoshi TOMINAGA
3rd Author's Affiliation Dept. of Electronics, Information and Communication Engineering, WASEDA University
Date 1997/7/24
Paper # MVE97-52
Volume (vol) vol.97
Number (no) 206
Page pp.pp.-
#Pages 7
Date of Issue