| Presentation | 2002/3/12 A Hardware Implementation of 128-bit Block Cipher : Camellia Tetsuya ICHIKAWA, Tomomi KASUYA, Mitsuru MATSUI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we report our hardware implementation of a 128-bit block cipher, Camellia, concentrating on a small implementation. As a result, our design achieves very small size, for example 6,374 gates on 0.18μmCMOS ASIC and 1,396 slices on Virtex1000E series, which work in 40 cycles/block. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cipher / Block Cipher / Camellia / Small Hardware |
| Paper # | ITS2001-149 |
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| Conference Information | |
| Committee | ITS |
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| Conference Date | 2002/3/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Intelligent Transport Systems Technology (ITS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware Implementation of 128-bit Block Cipher : Camellia |
| Sub Title (in English) | |
| Keyword(1) | Cipher |
| Keyword(2) | Block Cipher |
| Keyword(3) | Camellia |
| Keyword(4) | Small Hardware |
| 1st Author's Name | Tetsuya ICHIKAWA |
| 1st Author's Affiliation | Mitsubishi Electric Corporation Information Technology R&D Center() |
| 2nd Author's Name | Tomomi KASUYA |
| 2nd Author's Affiliation | Mitsubishi Electric Corporation Information Technology R&D Center |
| 3rd Author's Name | Mitsuru MATSUI |
| 3rd Author's Affiliation | Mitsubishi Electric Corporation Information Technology R&D Center |
| Date | 2002/3/12 |
| Paper # | ITS2001-149 |
| Volume (vol) | vol.101 |
| Number (no) | 732 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |