| Presentation | 2002/1/17 Miniaturization and Electric Power Reduction on a Hybrid Integrated Eight Channel SOAG Array Receptacle Module with Driver Circuits Takanori SHIMIZU, Tomoaki KATO, Jun-ichi SASAKI, Takara SUGIMOTO, Takemasa TAMANUKI, Hiroshi HATAKEYAMA, Satoshi AE, Akira TANABE, Tatsuya SASAKI, Akio FURUKAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have demonstrated the miniaturization and electric power reduction on a semiconductor optical amplifier gate (SOAG) array module for a terabit-ratc photonic packet switch. Small size and low power driver circuits have been developed by changing these circuits from bipolar to CMOS configuration, and by integrating 4-channel circuits on one chip. This module consists of 8-channel SOAG array switch, MT compatible receptacle connectors, SOAG driver circuits, and thermo-electric cooler in a ceramic package. This module size as 40×22×5.2mm, photonic switching power as 180mW, and high-speed switching response less than one nanosecond were successfully achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Semiconductor optical amplifier gate (SOAG) / Planar lightwave circuitn (PLC) / Photonic switching / CMOS |
| Paper # | 2001-PS-86,2001-OFT-83,2001-OPE-127,2001-LQE-113 |
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| Conference Information | |
| Committee | OFT |
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| Conference Date | 2002/1/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Optical Fiber Technology (OFT) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Miniaturization and Electric Power Reduction on a Hybrid Integrated Eight Channel SOAG Array Receptacle Module with Driver Circuits |
| Sub Title (in English) | |
| Keyword(1) | Semiconductor optical amplifier gate (SOAG) |
| Keyword(2) | Planar lightwave circuitn (PLC) |
| Keyword(3) | Photonic switching |
| Keyword(4) | CMOS |
| 1st Author's Name | Takanori SHIMIZU |
| 1st Author's Affiliation | Networking Research Labs.() |
| 2nd Author's Name | Tomoaki KATO |
| 2nd Author's Affiliation | Photonic and Wireless Devices Research Labs., NEC Corporation |
| 3rd Author's Name | Jun-ichi SASAKI |
| 3rd Author's Affiliation | Networking Research Labs. |
| 4th Author's Name | Takara SUGIMOTO |
| 4th Author's Affiliation | Networking Research Labs. |
| 5th Author's Name | Takemasa TAMANUKI |
| 5th Author's Affiliation | Photonic and Wireless Devices Research Labs., NEC Corporation |
| 6th Author's Name | Hiroshi HATAKEYAMA |
| 6th Author's Affiliation | Photonic and Wireless Devices Research Labs., NEC Corporation |
| 7th Author's Name | Satoshi AE |
| 7th Author's Affiliation | Photonic and Wireless Devices Research Labs., NEC Corporation |
| 8th Author's Name | Akira TANABE |
| 8th Author's Affiliation | Silicon Systems Research Laboratorics, NEC Corporation |
| 9th Author's Name | Tatsuya SASAKI |
| 9th Author's Affiliation | Photonic and Wireless Devices Research Labs., NEC Corporation |
| 10th Author's Name | Akio FURUKAWA |
| 10th Author's Affiliation | Networking Research Labs. |
| Date | 2002/1/17 |
| Paper # | 2001-PS-86,2001-OFT-83,2001-OPE-127,2001-LQE-113 |
| Volume (vol) | vol.101 |
| Number (no) | 586 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |