| Presentation | 2001/11/15 Scheduling Algorithm for Terabit Packet Switch Using Queuing State Information Masayuki Takase, Norihiko Moriwaki, Hidehiro Toyoda, Makoto Mori, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The Input-and-Output Buffer switch architecture is adequate for large-scale packet switches. However, increase of port speed and port number restrict scheduling processing time that is required to decide the combination of input ports and output ports. In this paper, we introduce parallel processing block switch architecture to solve above problem and suggest scheduling algorithm using queuing state information for this switch architecture. We evaluate effectiveness of this scheduling algorithm through computer simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Scheduler / Large-scale packet switch / Distributed parallel processing / Terabit / Simulation |
| Paper # | NS2001-164,CQ2001-76,TM2001-54 |
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| Committee | NS |
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| Conference Date | 2001/11/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Network Systems(NS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Scheduling Algorithm for Terabit Packet Switch Using Queuing State Information |
| Sub Title (in English) | |
| Keyword(1) | Scheduler |
| Keyword(2) | Large-scale packet switch |
| Keyword(3) | Distributed parallel processing |
| Keyword(4) | Terabit |
| Keyword(5) | Simulation |
| 1st Author's Name | Masayuki Takase |
| 1st Author's Affiliation | Research & Development Group, Hitachi, Ltd.() |
| 2nd Author's Name | Norihiko Moriwaki |
| 2nd Author's Affiliation | Research & Development Group, Hitachi, Ltd. |
| 3rd Author's Name | Hidehiro Toyoda |
| 3rd Author's Affiliation | Research & Development Group, Hitachi, Ltd. |
| 4th Author's Name | Makoto Mori |
| 4th Author's Affiliation | Research & Development Group, Hitachi, Ltd. |
| Date | 2001/11/15 |
| Paper # | NS2001-164,CQ2001-76,TM2001-54 |
| Volume (vol) | vol.101 |
| Number (no) | 442 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |