| Presentation | 2001/7/11 The architecture of a low-power and high-performance DSP "LIOT" developed for mobile telecommunications(LIOT:Low power Implementation for mObile Telecommunications) Ritsuko Tatematsu, Tohru Tsuruta, Norichika Kumamoto, Ryuta Tanaka, Shinya Kondoh, Hideki Yoshizawa, Nobuyuki Iwasaki, Kazuhiro Yamashita, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Having started the introductory service of the next generation mobile communications, mobile terminals capable of broadband data transmission become more attractive. To provide applications which utilize the breadth, visual data are promising, and a DSP that achieves high operation performances with a low power consumption is indispensable. To realize those applications, we designed a new DSP architecture LIOT(low power implementation for mobile telecommunications). The key technologies adopted in the DSP to reduce the power consumption are a SIMD-type parallel operation mechanism and a clock control mechanism. With these technologies, the power consumption per operation has been reduced to about 1/12 compared to our former LSI. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | processor architecture / parallel processing / DSP / IMT-2000 / broadband / mobile |
| Paper # | MoMuC2001-26 |
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| Conference Information | |
| Committee | MoMuC |
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| Conference Date | 2001/7/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Mobile Multimedia Communications(MoMuC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The architecture of a low-power and high-performance DSP "LIOT" developed for mobile telecommunications(LIOT:Low power Implementation for mObile Telecommunications) |
| Sub Title (in English) | |
| Keyword(1) | processor architecture |
| Keyword(2) | parallel processing |
| Keyword(3) | DSP |
| Keyword(4) | IMT-2000 |
| Keyword(5) | broadband |
| Keyword(6) | mobile |
| 1st Author's Name | Ritsuko Tatematsu |
| 1st Author's Affiliation | Fujitsu Laboratories Limited() |
| 2nd Author's Name | Tohru Tsuruta |
| 2nd Author's Affiliation | Fujitsu Laboratories Limited |
| 3rd Author's Name | Norichika Kumamoto |
| 3rd Author's Affiliation | Fujitsu Laboratories Limited |
| 4th Author's Name | Ryuta Tanaka |
| 4th Author's Affiliation | Fujitsu Laboratories Limited |
| 5th Author's Name | Shinya Kondoh |
| 5th Author's Affiliation | Fujitsu Laboratories Limited |
| 6th Author's Name | Hideki Yoshizawa |
| 6th Author's Affiliation | Fujitsu Laboratories Limited |
| 7th Author's Name | Nobuyuki Iwasaki |
| 7th Author's Affiliation | Fujitsu Kyusyu Digital Technology Limited |
| 8th Author's Name | Kazuhiro Yamashita |
| 8th Author's Affiliation | Fujitsu Kyusyu Digital Technology Limited |
| Date | 2001/7/11 |
| Paper # | MoMuC2001-26 |
| Volume (vol) | vol.101 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |