Presentation	2002/2/25 Design and Evaluation of Java Processor with Dynamic Instruction Conversion Mechanism for Embedded Systems MASATO SUZUKI, SHINJI KIMURA, KATSUMASA WATANABE,
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Abstract(in English)	Java processors are key for executing Java bytecodes in embedded systems, and are expected low hardware consumption and high executio is based on stack operations, and we can raise the efficiency by changing these codes into extended codes corresponding to RISC-like operations. Rewriting is done in cache and done in parallel with the direct execution of bytecode. By performing the execution and the conversion in parallel, we can manipulate complex conversions with low hardware cost. The paper shows the design and evaluation of the Java processor with the dynamic instruction conversion mechanism.
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Paper #	CPSY2001-109
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Committee	CPSY
Conference Date	2002/2/25(1days)
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Registration To	Computer Systems (CPSY)
Language	JPN
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Title (in English)	Design and Evaluation of Java Processor with Dynamic Instruction Conversion Mechanism for Embedded Systems
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1st Author's Name	MASATO SUZUKI
1st Author's Affiliation	Nara Institute of Science and Technology()
2nd Author's Name	SHINJI KIMURA
2nd Author's Affiliation	Nara Institute of Science and Technology
3rd Author's Name	KATSUMASA WATANABE
3rd Author's Affiliation	Nara Institute of Science and Technology
Date	2002/2/25
Paper #	CPSY2001-109
Volume (vol)	vol.101
Number (no)	671
Page	pp.pp.-
#Pages	8
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